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ADP3415–SPECIFICATIONS 1
(T A = 0 C to 100 C, V CC = 5 V, V BST – V SW = 5 V, SD = 5 V, C DRVH = C DRVL = 3 nF,
unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY (VCC)
Quiescent Current 2
I CCQ
Shutdown Mode
Operating Mode
V SD = 0.8 V
V SD = 5 V, No Switching
30
1.2
65
2
μ A
mA
UNDERVOLTAGE LOCKOUT
(UVLO)
UVLO Threshold
UVLO Hysteresis
V CCUVLO
V CCHUVLO
3.9
4.15
0.05
4.5
V
V
LOW-SIDE DRIVER SHUTDOWN
( DRVLSD )
Input Voltage High 3
V IH
2.0
V
Input Voltage Low 3
Propagation Delay 3, 4
(See Figure 3)
V IL
tpdl DRVLSD
tpdh DRVLSD
20
10
0.8
50
30
V
ns
ns
SHUTDOWN ( SD )
Input Voltage High 3
Input Voltage Low 3
V IH
V IL
2.0
0.8
V
V
INPUT (IN)
Input Voltage High 3
Input Voltage Low 3
V IH
V IL
2.0
0.8
V
V
THERMAL SHUTDOWN (THSD)
THSD Threshold
THSD Hysteresis
T SD
T HSD
T J = T A
T J = T A
165
10
° C
° C
HIGH-SIDE DRIVER (DRVH)
Output Resistance, DRVH – BST
1.5
3.5
?
Output Resistance, DRVH – SW
DRVH Transition Times 4
tr DRVH
V BST – V SW = 4.6 V
0.85
20
2.0
30
?
ns
(See Figure 4)
DRVH Propagation Delay 4, 5
tf DRVH
tpdh DRVH
V BST – V SW = 4.6 V, V DLY = 0 V
10
25
22
35
40
ns
ns
R DLY ≥ 120 k ?
100
200
ns
(See Figure 4)
tpdl DRVH
40
70
ns
LOW-SIDE DRIVER (DRVL)
Output Resistance, DRVL – VCC
1.6
3.0
?
Output Resistance, DRVL – GND
DRVL Transition Times 4
tr DRVL
V BST – V SW = 4.6 V
1.0
25
3.0
40
?
ns
(See Figure 4)
DRVL Propagation Delay 4, 5, 6
(See Figure 4)
SW Transition Timeout 7
tf DRVL
tpdh DRVL
tpdl DRVL
t SWTO
V BST – V SW = 4.6 V
V BST – V SW = 4.6 V
V BST – V SW = 4.6 V
V BST – V SW = 4.6 V
10
130
20
30
10
30
38
25
300
ns
ns
ns
ns
Zero-Crossing Threshold
V ZC
1.6
V
NOTES
1
2
3
4
5
6
7
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
Including I BSTQ quiescent current.
The signal source driving the pin must have 70 μ A (typ) pull-down strength to make a high-to-low transient, and 20 μ A (typ) pull-up strength to make a low-to-high
transient. The pin does not represent load (<100 nA) in static low (<0.8 V) and static high (>2.0 V) logic states (see TPC 3.) The pin can be driven with standard
TTL logic level source.
Guaranteed by characterization.
For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low.
Propagation delay measured until DRVL begins its transition.
The turn-on of DRVL is initiated after IN goes low by either V SW crossing a ~1.6 V threshold or by expiration of t SWTO .
Specifications subject to change without notice.
Rev. 6 | Page 2 of 10 | www.onsemi.com
–2 –
REV. B
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